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Principal Power Integrity Engineer (EMIR)
Location:
Westborough, MA
Description:
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactThe Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Principal Power Signal Integrity (PSI) engineering position. Commonly referred to as ASIC/SOC Power Analysis, Power Integrity Signoff or EMIR. Projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Timing, and other teams both at a local and global level.What You Can Expect In this hybrid role at a CCS site, you will be responsible for Power Integrity analysis and signoff for Static/Dynamic IR and EM at the SoC level Work with a variety of other disciplines and leaders in Physical Design, Integration, and Timing Define SoC power targets with the technical lead, including coordination with package team Managing and working with tool vendors on any related issues of the tool, or bring-up of the tool on a design Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation Responsible for managing tool and flow settings to insure the team is setup for success during analysisWhat We're Looking For Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. 5 years practical experience in Power Integrity Signoff (SoC level EMIR) and closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level Practical knowledge and experience on running, debugging, and providing solutions for Static and Dynamic IR and EM at all levels of SoC hierarchy Worked with both vector-less and vector modes of analysis at different phases of the SoC development Have collaborated with Physical Design team on strategies and techniques to reduce risks with IR and EM, in a correct by construction style Familiar with low power concepts and UPF, such as power gating and shutoff as it relates to power delivery and analysis Have some proficiency in Circuit, Physical Design and Timing Proficient in UNIX, and shell based scripting Knowledge and Experience in both TCL and Python languages Diligent, detail-oriented, and able to handle assignments with very little supervision Must possess good communication skills, be a self-driven individual and a good team playerPreferred Qualifications (in addition to the minimum qualifications) 10 years practical experience in Power Signal Integrity (ie. SoC level EMIR) and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level Practical experience with Cadence Voltus family of Signoff tools Collaborated with Physical Design team on correlating Early Rail Analysis in PD tools, with results from Signoff Have led a small team of PSI/EMIR engineers on SoC signoff, coordinating with PD and Timing Have been involved in developing the Power Distribution Network (PDN) power grid for an SoC Have led or participated in Power Integrity Signoff methodology and flow development Knowledge and experience with verifying electromigration limits and fixing electromigration related failures#LI-TM1Expected Base Pay Range (USD)139,100 - 205,790, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at XXXX@marvell.com.
Company:
Marvell Semiconductor
Posted:
April 2 on TopUSAJobs
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More About this Listing: Principal Power Integrity Engineer (EMIR)
Principal Power Integrity Engineer (EMIR) is a Engineering Engineer Job at Marvell Semiconductor located in Westborough MA. Find other listings like Principal Power Integrity Engineer (EMIR) by searching Oodle for Engineering Engineer Jobs.
Principal Power Integrity Engineer (EMIR) is a Engineering Engineer Job at Marvell Semiconductor located in Westborough MA. Find other listings like Principal Power Integrity Engineer (EMIR) by searching Oodle for Engineering Engineer Jobs.