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Principal CPU Architect, Fabric Congestion and QOS Management | Architect in Architecture & De1

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Principal CPU Architect, Fabric Congestion and QOS Management

Location:
Santa Clara, CA
Description:

Principal CPU Architect, Fabric Congestion and QOS Management page is loaded Principal CPU Architect, Fabric Congestion and QOS Management Apply locations US, CA, Santa Clara US, TX, Austin US, WA, Seattle time type Full time posted on Posted 2 Days Ago job requisition id JR1966795 NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's motivated by great technology-and outstanding people. We are leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world!We are seeking Principal CPU Performance Architects to build next generation CPU cores in support of a diverse array of NVIDIA products. If you are passionate about improving CPU performance through innovative CPU microarchitectural ideas, modeling them to demonstrate merit and then seeing them through implementation and Silicon bring-up; read on!What you'll be doing: Collaborate with other micro-architects and senior designers to propose and demonstrate the merit and limitations of innovative core CPU & Fabric microarchitectural features to drive up performance per area per power on various targeted workloads. Do the detailed performance modeling and debug, and studies to support inclusion of these features in the next generation core microarchitecture on the basis of performance, area or power improvement Partner with design and verification leads to iterate through specification, implementation in RTL and verification of the microarchitecture features to achieve target functionality, performance, frequency, area, power and verifiability Collaborate with Silicon Bring-up and Product teams to verify and debug the microarchitecture and its delivered performance A strong ability to communicate and drive to closure microarchitectural proposals both within the CPU Core and cross functionally with technical stakeholders across the SOC/SW/System both verbally and through presentations and documents.What we need to see: PhD in a relevant CPU and Fabric microarchitecture area or equivalent experience At least 10+ years of experience Prior experience innovating and architecting around Fabric Congestion Management & QoS features such as cache capacity and memory bandwidth apportioning mechanisms in large core-count systems is required. Prior experience in CPU, Fabric & SOC memory subsystem (caches, prefetchers etc.) large core-count SoCs and core CPU microarchitecture is required. A deep understanding of the state of the art of CPU microarchitecture and architecture with experience in one or more of the following broad areas: Memory Subsystem CPU micro-arch (MMU/TLB, Address Gen, Load/Store Units, L1, L2 caches, Prefetch) System / SOC Fabric & Memory Subsystem Uarch Large System Cache Coherency experience Experience in control theory design and mechanisms for dynamic feedback systems is highly desirable.Ways to stand out from the crowd: A technology enthusiast and passionate about what you do Strong collaborative and interpersonal skills, and a proven ability to effectively guide and influence the merits and drawbacks of the microarchitectural ideas to fellow micro architects, and implementation leads in a variety of media, both verbally and through presentations and documents.NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people on the planet working for us. If you're creative, passionate and self-motivated, we want to hear from you!The base salary range is $268,000 - $414,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits . NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. Similar Jobs (5) Lead Architect, GPU and SOC Simulation Platforms locations US, CA, Santa Clara time type Full time posted on Posted 30 Days Ago Senior Architect, GPU and SoC Modelling locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago About Us 0:00 -/ - 3:32 NVIDIA is a Learning Machine NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and the metaverse is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA . #J-18808-Ljbffr
Company:
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Principal CPU Architect, Fabric Congestion and QOS Management is a Architecture & Design Architect Job at Nvidia located in Santa Clara CA. Find other listings like Principal CPU Architect, Fabric Congestion and QOS Management by searching Oodle for Architecture & Design Architect Jobs.