This listing was posted on ITJobsWeb.
IP Design Verification Engineer
Location:
Santa Clara, CA
Description:
Job Description Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are This position is an IP Verification Engineer role in the Edge Acceleration IP group (EAIG), within the IP, Security and Client Product Group (ISCP) Who You Are Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Possess a Bachelor's degree in Electrical Engineering, Computer Engineering or similar discipline with at least 4 years of experience or MS degree in Electrical Engineering, Computer Engineering or similar discipline with at least 3 years of experience in complex IP or SOC validation. 2-3 years of IP/SoC verification experience and developing Testbench from scratch. Proficient in Verification languages like System Verilog and OVM/UVM. Experienced in Constraint random verification infrastructure, scoreboard, and checkers development. Practical experience of Debugging RTL code using simulation/emulation tools and UPF. Assertion and Functional Coverage coding experience . Candidate should have experience working independently with ownership. Preferred Qualifications: Adept in programming languages C, C++ and/or scripting perl/python. Sound understanding of modern Computer architecture. Verification fundamentals encompassing complex protocol verification (AXI, AHB, PCIe, OCP) or IO Bus protocols. Functional verification strategies for low power IP. Willing to work in a Dynamic Team-Oriented Environment. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Corporate Strategy Office is chartered to support the executive office in driving corporate initiatives, including near and long-term strategy, major cross-group decision making and ensuring cross-company alignment. To deliver to that mission, the team owns shaping, driving and synthesizing insights to directionally orient trends as well as long range strategic planning/visioning , cross company alignment and greenfield innovation. Communications are essential to drive alignment so there is a focus on communications, community and acumen development. The team is ccommitted to ensuring that Intel efforts are aligned to, and actively driving success toward the most impactful business strategies. Other Locations US, AZ, Phoenix; US, CA, Folsom Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0262554pca3lyuhf
Company:
Intel
Posted:
April 19 on ITJobsWeb
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More About this Listing: IP Design Verification Engineer
IP Design Verification Engineer is a Engineering Engineer Job at Intel located in Santa Clara CA. Find other listings like IP Design Verification Engineer by searching Oodle for Engineering Engineer Jobs.
IP Design Verification Engineer is a Engineering Engineer Job at Intel located in Santa Clara CA. Find other listings like IP Design Verification Engineer by searching Oodle for Engineering Engineer Jobs.