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Analog Engineer - Timing Analysis
Location:
Folsom, CA
Description:
Job Description Do Something Wonderful! The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful! Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver Mixed Signal solutions for products that impact customers lives? If so, come join us to do something wonderful. CEG (Client Engineering Group) designs and delivers the full range of client compute solutions on leading edge processes. The memory team within CEG develops cutting-edge High-Speed IO designs like LPDDR5, DDR5, PCIE Gen7, USB and Type C Phys for use in Intel's latest microprocessors. We own the design from architecture definition to tape-out and Post Silicon support covering all aspects of a Mixed Signal design from Analog circuit to RTL development and structural implementation. You will be responsible for, but not limited to:We are looking for an organized person with strong static timing analysis skills to run timing characterization for analog and mixed-signal circuits. The ideal candidate will have automation background which enables him/her to monitor and execute on many blocks concurrently. The candidate also should be methodical to ensure data consistency and correctness for the many circuits being analyzed across many different process/voltage/temperature corners. The candidate will also be expected to perform of perform static timing analysis on high-speed data path and clock crossings using industry standard STA tools.Experience in designing, developing, and building analog circuits in advanced process nodes for analog and mixed-signal IP's will be helpful. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: BS degree plus 4 years' experience minimum, or MS degree plus 3 years' experience minimum, or PhD plus 1 year experience minimum AND Experience doing static timing analysis work. Preferred Qualifications: Programming/scripting/automation skills Experience with analog circuit and/or standard cell characterization Good organization skills and ability to execute many instances of similar task concurrently. Understanding of architecture and integration aspects of DDR PHYs. Familiarity of LPDDR/DDR JEDEC specifications and related DDR Protocols. Understanding of design for yield and exposure to production challenges in latest technology process node. Experience with industry standard tools such as PrimeTime. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0254815pca3lyuhf
Company:
Intel
Posted:
April 6 on ITJobsWeb
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More About this Listing: Analog Engineer - Timing Analysis
Analog Engineer - Timing Analysis is a Engineering Engineer Job at Intel located in Folsom CA. Find other listings like Analog Engineer - Timing Analysis by searching Oodle for Engineering Engineer Jobs.
Analog Engineer - Timing Analysis is a Engineering Engineer Job at Intel located in Folsom CA. Find other listings like Analog Engineer - Timing Analysis by searching Oodle for Engineering Engineer Jobs.