This listing was posted on ITJobsWeb.
Staff CPU RTL Designer, Silicon
Location:
Mountain View, CA
Description:
About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.The US base salary range for this full-time position is $127,000-$187,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience. Responsibilities Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU. Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making. Deliver designs meeting Power, performance and area (PPA) goals with production quality. Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort. Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals. Requisition #: 79750973001474758pca3lyuhf
Company:
Google
Posted:
May 23 on ITJobsWeb
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More About this Listing: Staff CPU RTL Designer, Silicon
Staff CPU RTL Designer, Silicon is a Jobs Designer Job at Google located in Mountain View CA. Find other listings like Staff CPU RTL Designer, Silicon by searching Oodle for Jobs Designer Jobs.
Staff CPU RTL Designer, Silicon is a Jobs Designer Job at Google located in Mountain View CA. Find other listings like Staff CPU RTL Designer, Silicon by searching Oodle for Jobs Designer Jobs.