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Multi Project Shuttle (MPS) Program Manager
Location:
Hillsboro, OR
Description:
Job Description Intel Multi-Product Shuttle Program (MPS) provide an affordable, regular, predictable, and competitive silicon prototyping service for Intel internal divisions and Foundry designs. About the role: In this role, you will be required to interact and communicate with various teams and across organizations ranging from silicon design, design kits, Fab and assembly. You will be expected to actively participate in shuttle roadmap planning, passenger seat allocation, and tracking of project schedules. You will also be responsible for aligning technology collaterals and runset across multiple projects to meet manufacturing requirements. Your responsibilities will include but not be limited to: Coordinate shuttle roadmap planning and passenger support, manage parallel execution of MPS shuttle runs on multiple process technology nodes, reticle floorplan optimization, shuttle tapein and manufacturing.Work across a large, multi-site engineering team and negotiate with functional area managers as needed to resolve any execution issues. Coordinate usage of process design kit (PDK) to ensure shuttle passengers design meets the manufacturing requirements.Define, manage, and maintain a package of standard management indicators and communicate project status across teams.Manage and prioritize support requests, execution and inter-dependencies among multiple projects, teams and stakeholders. The successful candidate should exhibit the following behavioral traits: Self-disciplined, motivated, and innovative, with the ability to manage tasks of broad scope and complexity through all phases of the design cycle. Effective communication and presentation skills; attention to details in managing improvement projects. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications: Masters degree in Electrical Engineering, Computer Engineering, or other related field of study. 4+ years of relevant experience in silicon design and/or engineering management. Preferred qualifications: Prior working experience with MPW / Shuttle or test chip design tapeout desired. Proven track record of technical leadership and project execution management in the complete life cycle of a Silicon on Chip (SoC) or similar products from definition to design and tape-out. Working experiences of interfacing with process, design, and design automation teams. Good understanding of leading-edge process technologies, devices, and the interactions with circuit design. Familiar with SoC, CPU and custom (analog and digital) design styles, flows, tools, and methodologies. Familiar with EDA design software for VLSI layout and physical verification. Working fluency on process technology parameters, manufacturing steps, process characterization, physical design rules/runset. Familiarity with database management for large, multi-site design projects. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $123,139.00-$203,801.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0261923pca3lyuhf
Company:
Intel
Posted:
April 17 on ITJobsWeb
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More About this Listing: Multi Project Shuttle (MPS) Program Manager
Multi Project Shuttle (MPS) Program Manager is a Executive Program Manager Job at Intel located in Hillsboro OR. Find other listings like Multi Project Shuttle (MPS) Program Manager by searching Oodle for Executive Program Manager Jobs.
Multi Project Shuttle (MPS) Program Manager is a Executive Program Manager Job at Intel located in Hillsboro OR. Find other listings like Multi Project Shuttle (MPS) Program Manager by searching Oodle for Executive Program Manager Jobs.