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Logic Design and Verification Engineer
Location:
Santa Clara, CA
Description:
Tired of working on the same old boring stuff? How about doing something new to change theworld? How about working on an exciting next generation of computer memory architecture!- Job Description: - Logic design/synthesis/timing analysis or Logic Verification/Test Coverage - Responsible for design or verification, and presentation documents- Requirements: - MS EE/CS or BS EE/CS+2 years of experience - Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools - Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog/VHDL - Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM - Team player and an optimist: able to work with teams in multiple office sites.- Plus Skills: - Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI. - Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller - Fluent in System Verilog, SVA, C++ or assembly language - Experience with FPGA/emulator (Palladium/Veloce)PDN-9727ef74-1dd8-4140-979b-cd0dddb6d00a
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More About this Listing: Logic Design and Verification Engineer
Logic Design and Verification Engineer is a Engineering Engineer Job at FLC Technology Group located in Santa Clara CA. Find other listings like Logic Design and Verification Engineer by searching Oodle for Engineering Engineer Jobs.
Logic Design and Verification Engineer is a Engineering Engineer Job at FLC Technology Group located in Santa Clara CA. Find other listings like Logic Design and Verification Engineer by searching Oodle for Engineering Engineer Jobs.