This listing was posted on ITJobsWeb.
DFT Engineer
Location:
Folsom, CA
Description:
Job Description Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.Are you passionate about computer graphics and disrupting the industry with your innovation, and working with leading Engineers on Intel's latest GPU architecture. Do you love collaborating with diverse teams to help achieve best-In-class visual experiences that enable users to immerse themselves in a new visual future? Then the GPU Hardware IP team at Intel has opportunities for you. Our Hardware development team designs and validates the future processors that are the engines behind our GPUs. We are looking for a DFT Engineer to join our team who is ready to make significant impacts on the future of graphics and visual computing technology.As a member of the Graphics Hardware DFT group you will be responsible for but not limited to the following activities: You will work on the design, RTL/GLS validation, automation and/or timing analysis in the following DFT domains: TAP Controller, Scan, Array DFT (PBIST/MBIST), IO DFT, PLL DFT or HVM Reset. You will also contribute or be involved with trace pattern generation efforts as well as post-silicon enabling debug support and/or analysis of the DFT features and content types you are responsible for. Behavioral skills we are looking for: Strong written and verbal communication skills Leadership ability in driving execution Strong teamwork, problem solving and influencing skills Ability to work with different geographical locations Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelors Degree in Electrical/Computer Engineering or related STEM degree with 3+ years of industry experience in the following: Experience with ASIC design flow (SoC/IP design, integration, or verification) Design automation skills and/or proficiency in scripting languages (such as Python or Perl) Preferred Qualifications: Masters in Electrical/Computer Engineering or related STEM degree with 2+ years of industry experience. At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) EDA tools such as ATPG tools, Siemens Tessent Shell, Synopsis VCS simulation and/or debug tools Structural design flows, including timing, routing, placement or clocking analysis Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0256522pca3lyuhf
Company:
Intel
Posted:
April 13 on ITJobsWeb
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More About this Listing: DFT Engineer
DFT Engineer is a Engineering Engineer Job at Intel located in Folsom CA. Find other listings like DFT Engineer by searching Oodle for Engineering Engineer Jobs.
DFT Engineer is a Engineering Engineer Job at Intel located in Folsom CA. Find other listings like DFT Engineer by searching Oodle for Engineering Engineer Jobs.