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SOC Physical Design Engineer
Location:
Santa Clara, CA
Description:
SOC Physical Design Engineer page is loaded SOC Physical Design Engineer Apply locations US, California, Santa Clara time type Full time posted on Posted 7 Days Ago job requisition id JR0258427 Job Details:Job Description: - Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below! Life at Intel Diversity at Intel Intel NEX Cloud Networking (NCNG) team delivers best-in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. NCNG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform datacenter ecosystems.As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you.As a SOC Physical Design Engineer in NEX, you will Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyze results and makes recommendations to fix violations for current and future product architecture. Utilize expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimize design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.Responsibilities will include but not limited to: In this visible role, you will oversee the SOC physical implementation of a highly complex networking chip using cutting-edge technology nodes. Drive the execution of SoC design Physical design activities from synthesis to all the way to signoff. Work closely with the architect, RTL, and DFT teams to optimize/converge designs for better PPA. Channel analysis, feedthrough insertion, repeater/flop planning, custom route planning, and timing closure. Analysis of multiple power domains using standard power formats (UPF or CPF).Qualifications:What we need to see (Minimum Qualifications): Candidate must have a bachelor's degree in EE/CE/CS with 8+ years OR Master's degree in Computer science/Electrical or Computer Engineering with 6+ years of experience in: 5 + years' experience with Physical design/integration execution of complex SOCs/ASICs in 5nm and below. 5 + years' experience with microelectronic designs, semiconductor device physics, the CMOS process, and physical layout. 5 + years' experience in tools such as Design Compiler, ICC2/Innovus, Primetime, etc. 4+ years' experience of DFT, DFM, clocking, FEV, top-down and bottom-up design flows. 4+ years' experience scripting in PERL, TCL.How to Stand Out (Preferred Qualifications): Experience working with advanced process nodes such as 5nm and below Expert in physical design tools such as Design Compiler, Fusion Compiler, and Conformal. Experience in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification. Knowledge of floor planning, pin placement, and SOC integration. Experience with various types of external interfaces, such as DDR, PCIe, and similar Experience as a team lead.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research Amazing Benefits! Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. -Find more information about our Amazing Benefits here : https://jobs.intel.com/benefits Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: -US, California, Santa ClaraAdditional Locations:Business group:The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html Annual Salary Range for jobs which could be performed in US, California:$162,041.00-$259,425.00 S alary range dependent on a number of factors including location and experience. Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Similar Jobs (5) Physical Design Engineer locations 3 Locations time type Full time posted on Posted 30+ Days Ago Physical Design Engineer locations 3 Locations time type Full time posted on Posted 30+ Days Ago Physical Design Engineer locations 3 Locations time type Full time posted on Posted 30+ Days Ago Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click -here . #J-18808-Ljbffr
Company:
Intel
Posted:
March 5 on TopUSAJobs
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More About this Listing: SOC Physical Design Engineer
SOC Physical Design Engineer is a Engineering Design Engineer Job at Intel located in Santa Clara CA. Find other listings like SOC Physical Design Engineer by searching Oodle for Engineering Design Engineer Jobs.
SOC Physical Design Engineer is a Engineering Design Engineer Job at Intel located in Santa Clara CA. Find other listings like SOC Physical Design Engineer by searching Oodle for Engineering Design Engineer Jobs.